In semiconductor manufacturing processes, photolithography and etching techniques are commonly adopted to define patterns of a target layer. Generally, an integrated circuit layout is designed and outputted onto one or more photomasks. The integrated circuit layout is then transferred from the photomask(s) to a hard mask layer to form a mask pattern, and is subsequently transferred to a target layer from the mask pattern. However, with the advancing miniaturization and integration requirements of electronic or semiconductor devices, including memory devices such as dynamic random access memories (DRAMs), flash memories, static random access memories (SRAMs), and ferroelectric (FE) memories, the sizes such as line width and gap of patterns for such devices become finer and more miniaturized as well. Accordingly, the continual reduction in pattern size places ever-greater demands on the techniques used to prepare the patterned target layer.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.